1. Field of the Invention
The field of the invention generally relates to electronic design automation for integrated circuits and, more particularly, to systems and methods for optimizing the physical layout of elements in integrated circuit designs.
2. Background
Chip designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation of a chip design prior to prototyping or production. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. Typically, the chip designer builds up a circuit by inputting information at a computer workstation generally having high quality graphics capability so as to display portions of the circuit design as needed. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog(copyright) or VHDL, for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
Two of the primary types of components used in integrated circuits are datapaths and control logic. Control logic, typically random logic, is used to control the operations of datapaths. Datapath areas of the circuit perform functional operations, such as mathematical or other operations.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. The designer may also provide basic organizational information about the placement of components in the circuit using floorplanning tools. During these design states, the designer generally structures the circuit using considerable hierarchical information, and has typically provided substantial regularity in the design.
From the HDL or other high level description, the actual logic cell implementation may be determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then xe2x80x9cplacedxe2x80x9d (i.e., given specific coordinate locations in the circuit layout) and xe2x80x9croutedxe2x80x9d (i.e., wired or connected together according to the designer""s circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity. By application of a physical design process, the logic cells of the netlist file are placed and routed, resulting in a layout file.
However, for some HDL modules (for example, analog modules or high performance custom digital designs), logic synthesis may be impossible because of the lack of specific logic cells in the library. In these situations, from the HDL or other high level description, the actual circuit implementation is typically determined by custom layout design, which converts a netlist associated with the circuit design into a specific circuit layout implementation. The layout modules are then placed and routed. In this situation, the placement and routing software routines generally accept as their input a flattened netlist that has been generated by the custom layout process. This flattened netlist identifies the specific layout modules from a target device library, and describes the specific device-to-device connectivity. By application of a physical design process, the layout modules created from the netlist file are placed and routed, resulting in a production-ready layout file.
Device level layout editing for custom integrated circuit block design is a time-intensive task for present-day mixed-signal circuit designs. Mixed-signal designs may include combinations of CMOS, domino MOS logic, analog, and/or other MOS topologies. Custom layout techniques make the task of device level layout editing for mixed-signal designs a major bottleneck in the entire design process, due in large part to the specialized features required to optimize the design.
One aspect of device level layout is arriving at a physical ordering of devices. The transistors of a circuit can often be ordered in different configurations without changing their logical function. Properly ordering devices in a circuit can increase the circuit""s speed and reduce its layout area.
Module editing refers to a complex of layout editing and generation features that yield optimized layout for a set of devices and cells. The focus of module editing generally is device-level rather than shape-level. For MOS device level layout, module optimization methods comprise mainly device abutment and splitting. A primary optimization goal is to minimize layout area and unwanted interconnection parasitics. Minimizing area means that a maximum number of abutments should be created between the devices in the cell.
According to one well-known device layout technique, for a circuit design in which CMOS elements are present the transistors are placed in two parallel rows: the P-type transistors in one row, and the N-type transistors in another row. Power rails are routed along the two rows on the outside, and intracell routing is run between the rows. To minimize layout area, a primary goal is to place transistors in such a way that gate signals are aligned and the drain/source diffusions of adjacent transistors are abutted to the maximum extent possible, thereby reducing total diffusion area and minimizing the number of separations between diffusion strips.
While several algorithmic solutions have been proposed to optimize MOS device level layout, these solutions have limitations that restrict their utility. Prior solutions have generally been targeted toward particular circuit topologies, such as CMOS standard cells on the one hand, or specific analog circuits on the other. Furthermore, several of these solutions also suffer from inefficiencies in optimization speed.
It would therefore be advantageous to provide an improved circuit layout technique that results in rapid generation of optimal length chains and is applicable to any MOS circuit topology, including mixed-signal designs.
The present invention is directed in one or more aspects to methods for obtaining optimal layouts for integrated circuit design according to a custom physical design process.
In a first aspect of the invention, a method is provided for creating layouts characterized by optimal-length chains for different types of MOS circuit designs, including mixed-signal MOS designs. In a second separate aspect of the invention, a chaining engine having a device library and operating on a computer converts a circuit representation such as a netlist file into a layout file characterized by optimal-length chains, and such conversion may be accomplished in linear time. From a circuit representation, a bipartite graph (such as a graph having properties of an Euler graph) is prepared. A starting node in the bipartite graph is selected according to enumerated Euler trail algorithm rules. A constraint greedy walk is conducted to generate layout chains, and is preferably repeated until the bipartite graph is exhausted of edges, at which point the resulting layouts are returned. Advantageously, a single optimal layout solution can be obtained without enumerating all the possible layout options, resulting in a considerable speed advantage over conventional techniques. The disclosed chaining methods may be used, for example, in both customizing layouts and in creating automated layouts when enhanced with optional partitioning and/or folding capabilities.
In a third separate aspect of the invention, any of the foregoing aspects are contemplated in combination for additional advantage.